Native IR And Machine Model

Native IR is the verified low-level contract for 0x0 native performance work.

It sits after typed/effect checking and before machine-code emission, object

emission, linker input generation, or freestanding firmware image production.

The authoritative machine-readable files are:

• native-ir/schema.tsv: native IR envelope fields;
• native-ir/opcodes.tsv: supported opcodes and their effects;
• native-ir/machine-types.tsv: primitive, pointer, address, aggregate, flags,

and deferred vector shapes;

• native-ir/targets.tsv: target triples, CPU, ABI, endian, data layout,

relocation model, code model, and target features;

• native-ir/memory-model.tsv: pointer provenance, address spaces, volatile

MMIO, alias, and lifetime rules;

• native-ir/lowering-invariants.tsv: required typed/effect and backend

lowering invariants;

• native-ir/verification-cases.tsv: positive and negative verifier fixtures;
• compat/native-ir-contract.tsv: release-facing contract evidence.

Position In The Pipeline

Native IR is not source syntax. It is a compiler-owned artifact derived from

typed/effect IR or an audited equivalent typed lowering. Backends may consume

native IR directly, or a backend may consume an audited lowering from native IR

when that backend has explicit evidence.

The invariant is simple: once native IR verifies, native backends get a single

typed machine model for blocks, values, calls, memory operations, control flow,

static data, traps, source spans, effects, and target features.

Machine Model

The first target rows are:

• x86_64-unknown-linux-elf: hosted ELF with the current

zero-x86_64-sysv-v0.1 ABI;

• sim-cortex-m0: freestanding embedded target profile with the

zero-freestanding-v1 ABI and QEMU-or-equivalent emulator requirement.

Every target row names:

• target triple;
• CPU family;
• ABI;
• endianness;
• pointer width;
• data layout;
• relocation models;
• code models;
• supported target features.

Memory And Volatile Rules

Pointers use concrete address spaces, for example ptr[stack,i64],

ptr[heap,i64], or ptr[mmio,i32].

The verifier rejects pointer casts that change address spaces unless a target

rule explicitly allows the cast. No current target allows generic memory to be

cast into MMIO.

Volatile MMIO operations must:

• use a ptr[mmio,T] pointer;
• use address_space=mmio;
• use ordering=volatile;
• appear in a function with the hardware effect.

Optimizers must not delete, duplicate, merge, split, speculate, or reorder

volatile operations relative to other volatile operations.

Verifier

Run:

make native-ir-check

This bounded gate validates the schema files and fixtures. It does not run

native code generation, self-hosting, release packaging, emulator matrices, or

benchmark matrices.

Stable verifier diagnostics include:

• NATIVE_IR_SCHEMA: malformed native IR envelope;
• NATIVE_IR_TARGET: unknown target;
• NATIVE_IR_ABI: ABI does not match selected target;
• NATIVE_IR_LAYOUT: data layout does not match selected target;
• NATIVE_IR_TARGET_FEATURE: unsupported required target feature;
• NATIVE_IR_CONTROL_FLOW: missing entry block, missing branch target, missing

terminator, or instruction after terminator;

• NATIVE_IR_TYPE: unknown type, duplicate value, use before definition, or

return mismatch;

• NATIVE_IR_POINTER_CAST: illegal pointer cast;
• NATIVE_IR_VOLATILE: illegal volatile operation;
• NATIVE_IR_EFFECT: operation requires an effect missing from the function;
• NATIVE_IR_SPAN: instruction lacks a stable source span.

Current Boundary

Milestone 1 defines and verifies the contract. Later milestones implement

freestanding runtime profiles, monomorphization, strictness analysis, inlining,

tail calls, native machine code generation, tiny binaries, hardware access, and

release benchmark evidence.