Native Machine Code Backend

This page documents the bounded native machine-code backend evidence for 0x0.

It covers instruction selection, register allocation, frame lowering, block

layout, direct ELF/object emission, disassembly evidence, symbols, sections,

relocations, conformance, and benchmark records.

Run the bounded gate with:

make native-codegen-check

The gate does not run the full release or self-host matrix. It validates the

source-owned native backend evidence and the release reports listed below.

Evidence Files

• native-codegen/schema.tsv;
• native-codegen/instruction-selection.tsv;
• native-codegen/register-classes.tsv;
• native-codegen/frame-policies.tsv;
• native-codegen/emission-artifacts.tsv;
• native-codegen/verification-cases.tsv;
• native-codegen/fixtures/valid-native-codegen.json;
• release/native-codegen-report.tsv;
• release/native-codegen-disassembly.tsv;
• release/native-codegen-symbols.tsv;
• release/native-codegen-sections.tsv;
• release/native-codegen-relocations.tsv;
• release/native-codegen-conformance.tsv;
• perf/native-codegen-benchmarks.tsv;
• compat/native-codegen-contract.tsv;
• tools/native-codegen-check.py.

Instruction Selection

Instruction selection maps verified native IR operations onto target

instructions. The current native-codegen contract covers baseline x86_64

integer, branch, memory, volatile, direct-call, return, and required-tail

lowering.

Every instruction names a required target feature. The checker rejects an

instruction when the target does not advertise that feature:

NATIVE_CODEGEN_TARGET_FEATURE

Register Allocation

Register allocation evidence records register classes, physical registers,

callee-save use, rematerialization, and spills. Spills must fit the configured

budget and use aligned stack slots.

Important diagnostic:

NATIVE_CODEGEN_REGISTER

Frame Lowering

Frame evidence covers frame size, stack alignment, red-zone use, callee-save

state, no-unwind policy, stack maps, and interrupt-safe frames. Interrupt-safe

frames must not use the red zone.

Important diagnostic:

NATIVE_CODEGEN_FRAME

Block Layout And Disassembly

Block layout records branch lowering, layout order, alignment, scheduling

policy, constant islands, and literal pools.

release/native-codegen-disassembly.tsv records the disassembly evidence used

by the gate. Volatile instructions must have disassembly rows with stable

ordering evidence, and required tail calls must have jump evidence and zero

stack growth.

Important diagnostics:

NATIVE_CODEGEN_VOLATILE
NATIVE_CODEGEN_TAIL

ELF/Object Emission

The native backend evidence includes deterministic sections, symbols, and

relocations:

• release/native-codegen-symbols.tsv;
• release/native-codegen-sections.tsv;
• release/native-codegen-relocations.tsv.

External calls in object output require relocation evidence. Unsupported or

missing relocation evidence fails closed:

NATIVE_CODEGEN_RELOCATION

Conformance And Diagnostics

release/native-codegen-conformance.tsv records the bounded corpus:

• main-i64: differential integer result evidence;
• tail-required: required-tail zero-stack-growth evidence;
• mmio-volatile: volatile disassembly evidence;
• object-external-call: object relocation evidence;
• bare-metal-smoke: documented unsupported-target diagnostic for the

bare-metal target until the hardware milestone closes.

The bare-metal row is not a silent success. It is a documented diagnostic:

NATIVE_CODEGEN_TARGET_UNSUPPORTED

What This Does Not Overpromise

This gate proves the current native machine-code backend evidence for the

listed target profiles. Later milestones still own small-binary post-link

optimization, full bare-metal output, hardware emulator execution, compile-time

caching, and final release-wide verification.